Increasing levels of integration of integrated circuit chips reduces the chip count of a functional circuit, while significantly increasing the I/O count of the individual integrated circuits making up the functional circuit. This drive for increased circuit and component density in the individual integrated circuit chips leads to a parallel drive for increased circuit and component density in the printed circuit boards carrying the chips and in the assemblies using them.
Many applications in electronic packaging including laminate chip carriers are being constrained in their ability to escape the desired number of I/O. These constraints include line widths, line spaces, plated through-hole diameters and plated through-hole capture pad diameters. Plated through-holes are typically limited in their size by the ability of small drills, and the inability to plate holes of high aspect ratios (hole length/divided by hole diameter). Line widths/spaces are typically limited by photo lithographic constraints including the tendency for yields to decrease with decreased line widths.
The increase circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above plated through-holes highly desirable. This is especially the case when the density of the plated through-holes required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the plated through-hole grid.
This problem is especially severe with fine pitch ball grid array components (BGA) and flip chip attach (FCA) integrated circuits.
It would therefore be desirable to provide for the tenting of plated through-holes by a dielectric layer.